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wireless components fm car radio ic with pll tua 4401k v 2.1 specification 17.02.00 ds 1
edition 03.99 published by infineon technologies ag i. gr., sc, balanstra?e 73, 81541 mnchen ? infineon technologies ag i. gr. 08.03.00. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits im- plemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you ? get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of the infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life- support device or system, or to affect its safety or effectiveness of that device or system. 1. 2life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain human life. if they fail, it is reasonable to assume that the health of the user may be endangered. abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? -2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? - 2, sicofi ? -4, sicofi ? -4c, slicofi ? are registered trademarks of infineon technologies ag. ace ? , asm ? , asp ? , potswire ? , quadfalc ? , scout ? are trademarks of infineon technologies ag. revision history: current version: 02.00 previous version:data sheet 23.09.1999 page (in previous version) page (in current version) subjects (major changes since last revision) 3-7 3-7 functional description pin 41 corrected 3-11 3-11 functional description pin 41 corrected 5-3 5-3 sequence tests 310 to 317 changed (item) 5-5 5-5 values attack current changed 5-5 5-5 values recovery current changed 5-5 5-5 values detector characteristic changed
productinfo product info wireless components specification, 17.02.00 package tua 4401k productinfo general description the tua 4401k is the first infineon carradio ic using bicmos technol- ogy. the combination of an analog fm receiver circuit and a digital pll syn- thesizer on the same chip reduces the over all pin count in comparison to two separate ic ? s and in addition the number of necessary external compo- nents. this gives the flexibility both for high performance and low cost appli- cations. the recommended applications for this device are fm only carradios and back- ground receivers, capable for all world standards. features double balanced rf mixer with low noise figure, high ip3 and wide dynamic range strictly symmetrical rf circuitry if amplifier with adjustable gain double frequency 1st lo option 7 stage limiter amplifier with db linear fieldstrength output low distortion coincidence demodulator multipath detector with analog output cmos pll-synthesizer resolution between 100 khz and 6.25khz search tuning stop with if counter and fieldstrength/multipath evaluation adc ? s for fieldstr. and multipath detector i 2 c bus operation applications fm only car radio receiver, back- ground receiver ordering information type ordering code package tua 4401k mqfp-44
1 table of contents 1 table of contents 1-1 2 product description 2-1 2.1 general description 2-2 2.2 applications 2-3 2.3 features 2-3 2.4 package outlines 2-4 3 functional description 3-1 3.1 pin configuration 3-2 3.2 block diagram 3-12 3.3 functional block diagram 3-13 3.4 circuit description 3-14 4 applications 4-1 4.1 application and circuits 4-2 5 reference 5-1 5.1 electrical data 5-2 5.1.1 absolute maximum range 5-2 5.1.2 operating range 5-2 5.1.3 ac/dc characteristics 5-3 5.2 phase detector outputs 5-7 5.3 bus interface 5-8 5.4 i2c bus timing 5-13
2 product description 2.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 contents of this chapter
product description 2 - 2 tua 4401k wireless components specification, 17.02.00 2.1 general description the tua 4401k is the first infineon carradio ic using bicmos technology. the combination of an analog fm receiver circuit and a digital pll synthesizer on the same chip reduces the over all pin count in comparison to two separate ic ? s and in addition the number of necessary external components. this gives the flexibility both for high performance and low cost applications. the recommended applications for this device are fm only carradios and back- ground receivers, capable for all world standards. tua 4401k features: frontend high level, high impedance mixer input with improved dynamic range high input / output 3rd order intercept point integrated prestage agc generation and control for pin diodes and mos tetrode bus controlled agc threshold 2 pin 1st local oscillator with improved low phase noise, internally coupled to pll. double frequency operation possible strictly symmetrical rf parts pll with fast acquisition mode resolution 100 khz, 50 khz, 25 khz, 12,5 khz, 10 khz and 6.25 khz high running (61.5 mhz) crystal oscillator to avoid interference with bus controlled adjustment if amplification, demodulation and sts low noise if amplifier gain adjust with dc control voltage or serial bus possible 7 stage if limiter with extended fieldstrength range suitable for the if fre- quency range of 10.7 mhz ... 21.4 mhz fieldstrength dc output and adc output available low distortion coincidence demodulator (using short loop afc principle) with mpx output wideband multipath detector with analog output and adc output if counter for search tuning stop with selectable if center frequency, window width and programmable thresholds for fieldstrength and multipath evaluation sts informations -in window-,-below-,-beyond- available
product description 2 - 3 tua 4401k wireless components specification, 17.02.00 i 2 c bus i 2 c bus (2 wire, fast mode device with 400 kbit/s) operation possible bus interface with low threshold voltage schmitt trigger inputs for interfac- ing 3v or 5v microprocessors 2.2 applications fm only car radio receiver, background receiver 2.3 features double balanced rf mixer with low noise figure, high ip3 and wide dynamic range strictly symmetrical rf circuitry double frequency 1st lo option if amplifier with adjustable gain 7 stage limiter amplifier with db linear fieldstrength output low distortion coincidence demodulator multipath detector with analog output cmos pll-synthesizer resolution between 100 khz and 6.25khz search tuning stop with if counter and fieldstrength/multipath evaluation adc ? s for fieldstr. and multipath detector i 2 c bus operation
product description 2 - 4 tua 4401k wireless components specification, 17.02.00 2.4 package outlines mqfp 44
3 functional description 3.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.3 functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.4 circuit description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 contents of this chapter
functional description 3 - 2 tua 4401k wireless components specification, 17.02.00 3.1 pin configuration pin_config.wmf figure 3-1 ic pin configuration fs_adc 34 35 36 37 38 123456 789 39 40 41 42 43 44 10 11 22 21 20 19 18 17 16 15 14 13 12 33 32 31 30 29 28 27 26 25 24 23 mqfp44 mpa_adc station_detect scl sda vrefd5v vrefd3v xtal_div6 port_2 quartz1 quartz2 vccif ifampc ifoutfm ifin ifinfm gndif1 vrefrf if1 if2 agcout_p fm2 fm1 pre_cap vccrf osc2 osc1 gndrf pd_0 pda port_1 gndd vccd fm ifin fm ibias gndif2 mpxout fsout mpa_in mpacap mpa_out demafc ph02 ph01 table 3-1 pin configuration pin no. symbol equivalent i/o-schematic function 1 2 fs_adc mpa_adc 1: adc input fieldstrength 2: adc input multipath detector 5 pf gndd +5v +5v 1 2
functional description 3 - 3 tua 4401k wireless components specification, 17.02.00 table 3-1 pin configuration (continued) pin no. symbol equivalent i/o-schematic function 3 station_detect 3: if counter output station detector 4 scl 4: i 2 c bus clock input 5 sda 5: i 2 c bus data in/output 6 vrefd5v 6: reference voltage digital section (5v) 7 vrefd3v 7: reference voltage digital section (3v) 8 xtal_div6 8: crystal oscillator auxil- iary output (10.25 mhz) +5v gndd 3 +5v gndd + 5v 4 330 gndd + 5v 5 330 v+ 3v gndd 2k 200ff 8
functional description 3 - 4 tua 4401k wireless components specification, 17.02.00 table 3-1 pin configuration (continued) pin no. symbol equivalent i/o-schematic function 9 port_2 9: switch port output 2(open drain) 10 11 quartz1 quartz2 10: reference oscillator input / crystal 11: reference oscillator input / crystal 12 vccd 12: positive power supply voltage for serial bus and synthesizer 13 gndd 13: ground for serial bus and synthesizer 14 port_1 14: switch port output 1 (open drain) + 5 v gndd 9 330 2,5 k 5k 5k 10 11 + v + 5 v gndd 14 330
functional description 3 - 5 tua 4401k wireless components specification, 17.02.00 table 3-1 pin configuration (continued) pin no. symbol equivalent i/o-schematic function 15 pda 15: pll phasedetector output analog (tuningvoltage) 16 pd_0 16: pll chargepump output (phase detector tristate chargepump output) 17 gndrf 17: ground for rf part gndd pd vccd +5 v 15 3k 12 i pda pd +5 v +5 v +5 v 16 nc
functional description 3 - 6 tua 4401k wireless components specification, 17.02.00 table 3-1 pin configuration (continued) pin no. symbol equivalent i/o-schematic function 18 19 osc1 osc2 18: 1st local oscillator circuit 19: 1st local oscillator circuit 20 vccrf 20: positive power supply voltage for rf part 21 pre_cap 21: prestage agc time con- stant capacitor; output for mos tetrode gate 2 + v 18 + v 19 2,2v + v 21 6,4v
functional description 3 - 7 tua 4401k wireless components specification, 17.02.00 table 3-1 pin configuration (continued) pin no. symbol equivalent i/o-schematic function 22 23 fm1 fm2 22: fm 1st mixer symmetrical input 23: fm 1st mixer symmetrical input 24 agcout_p 24: prestage agc current output for pin diode nor- mal polarity + v 2,6 v 2,0k 2,0k 25 26 22 23 24 +v
functional description 3 - 8 tua 4401k wireless components specification, 17.02.00 table 3-1 pin configuration (continued) pin no. symbol equivalent i/o-schematic function 25 26 if2 if1 25: 1st mixer output (open collector) 26: 1st mixer output (open collector) 27 vrefrf 27: reference voltage rf section (4.8v) 28 gndif1 28: ground for if amplifier 29 30 ifinfm ifin 29: 10.7 mhz if amplifier input 30: 10.7 mhz if amplifier operation point + v 2,6 v 2,0k 2,0k 25 26 22 23 30 29 + v 17k 17k 330 3,8v
functional description 3 - 9 tua 4401k wireless components specification, 17.02.00 table 3-1 pin configuration (continued) pin no. symbol equivalent i/o-schematic function 31 ifoutfm 31: 10.7 mhz if amplifier out- put 32 ifampc 32: 10.7 mhz if amplifier dc gain control adjust block- ing capacitor 33 vccif 33: positive power supply voltage for if amplifier 34 35 fmifin fmifbias 34: fm limiter input 35: fm limiter input bias decoupling capacitor 36 gndif2 36: ground for limiter ampli- fier + v 330 31 + v 32 8k + v 330 33k 33k 35 34 5,5 v
functional description 3 - 10 tua 4401k wireless components specification, 17.02.00 table 3-1 pin configuration (continued) pin no. symbol equivalent i/o-schematic function 37 mpxout 37: fm mpx signal output 38 fsout 38: fieldstrength output 39 mpa_in 39: multipath detector input 37 +v 34k 66k + v + v 38 nc + v 86k 39
functional description 3 - 11 tua 4401k wireless components specification, 17.02.00 table 3-1 pin configuration (continued) pin no. symbol equivalent i/o-schematic function 40 mpacap 40: multipath detector rectifier capacitor 41 mpa_out 41: multipath detector output 42 demafc 42: demodulator afc block- ing capacitor 43 44 ph02 ph01 43: demodulator circuit 44: demodulator circuit + v 40 + v 41 + v 76k 3,5v 42 15p + v 4,8v 15k 43/44
functional description 3 - 12 tua 4401k wireless components specification, 17.02.00 34 35 36 37 38 123456 fm ifin fmifbias gndif2 mpxout fsout vccif ifampc ifoutfm ifin ifinfm gndif1 fs_adc mpa_adc station_detect scl sda vrefd5v vrefrf if1 if2 mpa_ain mpacap mpa_out vrefd3v xtal_div6 port_2 789 39 40 41 demafc ph02 ph01 agc_out_p fm2 quartz1 quartz2 42 43 44 10 11 22 21 20 19 18 fm1 pre_cap vccrf osc2 osc1 gndrf pd_0 pda 17 16 15 port_1 gndd vccd 14 13 12 33 32 31 30 29 28 27 26 25 24 23 if am p vref fm lim / dem / fs / m p-det mixer 1st lo preset agc pll synth. serial bus if counter adc/dac cryst osc 3.2 block diagram funct_block.wmf figure 3-2 main block diagram
functional description 3 - 13 tua 4401k wireless components specification, 17.02.00 3.3 functional block diagram funct_block.wmf figure 3-3 functional block diagram gate2 fm pin diode 1 prest agc fm osc buffer / div 2 osc 1. lo v ref rf n counter soccar bus charge pump pd port r counter adj crystal div/6 clock counter if counter 7 bit adc gate time counter mp det. afc loop dem fm if limiter field strength v ref if if amp gain adj. 4 bit dac if gain 2 bit dac prest. agc thresh. 21 24 22 23 25 26 20 18 19 27 17 5 4 15 16 14 9 10 11 8 12 67 3 1 2 38 41 40 39 42 43 44 35 34 31 36 33 28 32 30 29 data bus 10.7 mhz cer filter 10.7 mhz cer filter 10.7 mhz cer filter or amp external mos tetrode v cc if mp det in mpx out mp det ou t field- strength station_detect v ccd p2 p1 sda scl v cc rf 13 37
functional description 3 - 14 tua 4401k wireless components specification, 17.02.00 3.4 circuit description the tua 4401k is a one chip fm car radio system consisting of rf frontend, gain adjustable if amplifier, fm-if limiter amplifier, demodulator, pll synthe- sizer, if counter for sts and adc ? s for fieldstrength and multipath detector. the serial bus is a i 2 c type. 1. fm frontend the frontend consists of a two pin varactor tuned oscillator, a double bal- anced mixer and a prestage agc control circuit. the mixer has an improved intermodulation behaviour and converts the rf signal to the 10,7 mhz if range . two inputs allow both symmetrical and unsymmetrical operation. the integrated agc stage for prestage control drives mosfets as well as pin diodes a with cur- rent driver. the agc threshold can be set with a serial bus controlled 2 bit dac. for background receiver application the oscillator is able run at double frequency, a subsequent frequency divider by 2 is acti- vated by serial bus to provide the correct mixer frequency. 2. fm if amplifier after the mixer an if amplifier is present for if post amplification. input and output impedance are both 330 ohms for matching with ceramic filters. for adjusting the over all gain the if amplifier gain can be adjusted with a serial bus controlled 4 bit dac. 3. fm limiter and demodulator the fm if amplifier includes a seven stage capacitive coupled limiter ampli- fier and a fieldstrength generator with high linearity and increased dynamic range. the coincidence demodulator has an additional afc short loop cir- cuit with integrated varactor diode in parallel to the external tank circuit to improve the distortion bahaviour in case of detuning. 4. multipath detector a wideband multipath detector with analog output is available. 5. a/d converter for fieldstrength and multipath detector the 7 bit a/d converter has two input channels and works as successive approximation converter. the conversion time for both input signals is t = 32 s. the 7-bit digital-words from both channels (14 bit) are read out together via bus into two bytes with the read subaddress 82h. the input voltage range for both channels is 0...vrefd5v. 6. if counter and multipath/fieldstrength evaluation for sts fm center frequencies ar available in two ranges set by bit d7 in subaddress 05h. for d7=1 the range of centerfrequency is 20.800 mhz...22.3875 mhz in 128 steps (12.5 khz per step). for d7=0 the range of centerfrequency is 10.400 mhz...11.1937 mhz in 128 steps (6.25 khz per step). the gate time is adjustable in 8 steps from 320us...40.96ms and the toler- ance of the accepted count value, the window is adjustable in 5 steps from +/- (6.25khz...100khz) for d7=0 in sub-address 05h and
functional description 3 - 15 tua 4401k wireless components specification, 17.02.00 +/- (12.5 khz...200 khz) for d7=1 in subaddress 05h. the results if_cent and if_window are read out via bus (read-subaddress 82h&83h) or pin station_detect. if the if frequency is into the preselected window, station_detect goes from high to low level. if the if frequency is outside the preselected window, station_detect is high. the bit if_window is a hint if-frequency that is to low (if_window=high) or is to high (if_window=low). in addition to the frequency measurement, thresholds for multipath and field- strength voltages can be programmed via bus (subaddress 0bh). station_detect will only go to low level in case of field-strength and multipath voltages are beyond the thresholds and the frequency is inside the window. when setting the thresholds to zero multipath and fieldstrength evaluation is disabled. 7. crystal oscillator a master crystal oscillator provides all necessary clock frequencies for the whole ic. a 61.5 mhz crystal is used in 3rd harmonic mode. the oscillator frequency can fine tuned with a serial bus controlled 4 bit d/a converter. the crystal frequency is used as reference frequency for the pll oscillator and if counter. it is also used as clock for the adc ? s. finally the crystal fre- quency divided by 6 (10.25 mhz) is available at a pin as low pass filtered voltage, it can be disabled with the serial bus. 8. output ports port_1 / 2 are nmos open drain outputs. 9. i 2 c bus the TUA4401K supports the i 2 c bus protocol (2 wire). all bus pins ( scl, sda) are schmitt triggered input buffer for 3v or 5v c. the bit stream begins with the most significant bit (msb), is shifted in (write mode) on the low to high transition of clk and is shifted out (read mode) on the high to low transition of clk i 2 c bus mode: data transition: data transition on the pin sda must only occur when the clock scl is low. sda transitions while scl is high will be interpreted as start or stop condi- tion. start condition (sta): a start condition is defined by a high to low transition of the sda line while scl is at a stable high level.this start condition must precede any command and initiate a data transfer onto the bus. stop condition (sto): a stop condition is defined by a low to high transition of the sda while the scl line is at a stable high level. this condition terminate the communication between the devices and forces the bus interface into the initial conditions.
functional description 3 - 16 tua 4401k wireless components specification, 17.02.00 acknowledge (ack): indicates a successful data transfer. the transmitter will release the bus after sending 8 bit of data. during the 9th clock cycle the receiver will pull the sda line to low level to indicate it has receive the 8 bits of data correctly. data transfer write mode: to start the communication, the bus master must initiate a start condition, followed by the 8bit chip address (write). the chip address for the tua 4401 is fixed as ? 1100110 ? (msb at first). the last bit (lsb=a0) of the chip address byte defines the type of operation to be performed: a0=1, a read operation is selected and a0=0, a write operation is selected. after this comparison the tua 4401 will generate an ack. after this device addressing the desired subaddress byte and data bytes must be followed. the subaddresses determines which one of the 9 data bytes (00h...07h, 0bh) is transmitted first. at the end of data transition the master must be generate the stop condition. data transfer read mode: to start the communication in the read mode, the bus master must initiate a start condition, followed by the 8bit chip address (write: a0=0), followed by the sub address read (82h/83h), followed by the chip address (read: a0=1). after that procedure the 16bit/8bit data register 82h/83h is read out. after the first 8 bit read out, the up mandatory send low during the ack-clock. after the second 8 bit read out the up mandatory send high during the ack-clock. at the end of data transition the master must be generate the stop condition. 10.pll synthesizer r / n counter the tua 4401k has 2 identical 16bit counter for r and n path. input fre- quency for the r-counter is the buffered xtal-frequency (61.5mhz). tuning steps can be selected by the 16bit r-counter from f r = 6.25khz...100khz. input frequency for the n-counter is the buffered lo-frequency (in fm mode 98.2mhz...118.7mhz). three state phase comparator the phase comparator generates a phase error signal according to phase difference between f r (r counter output) and f n (n counter output).this phase error signal drives the charge pump current generator. charge pump the charge pump generates signed pulses of current. 4 current values are available. loop amp the integrated rail to rail loop amplifier allows an active loop filter design with external components. two modes are available with status bit d11: high speed and normal mode.
4 applications 4.1 application and circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 contents of this chapter
applications 4 - 2 tua 4401k wireless components specification, 17.02.00 4.1 application and circuits fm only car radio receiver, background receiver 4401k_test_circ.wmf figure 4-1 test circuit TUA4401K 1 2 3 4 56 7 89 1011121314151617181920 2122 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 fs_adc if-cent scl sda vref5v vref3v xtal/6 port1 r-counter 61.5mhz vccd port2 n-counter pd pd_0 1n 1n 22k 22k 4,7k bb914 1n 1uh bar63 local oscill vccrf fm1 fm2 precap 10uh 1k 1n 10n 100 agcout_p mix1 mix2 vrefrf ifinfm ifin ifout_fm ifampc vccif fmifin fmifbias mpx-out fieldstrength 10n 10 330 + - 33n 100 4,7k 22n 1k 1n 51 22n 1k 22n 330 +- 1k 100uh 22n 22n 100 rf-source 10.7mhz 22n 51 22n 1k 1n 51 mdp-cap 68p toko 600bns-a1004hm demafc 1k 1uf mpd-out mdp-in 47n 100 mpa_adc 33n 33n 10k 10k + - 1k 6,8n 150p 33k 1k 10n 3,3k 22n 22n 3,3k 3,3k 51 200khz audio measure system rf-measure 10.7mhz rf-source 110.7mhz rf-measure 10.7mhz toko 218fcs-2166n rf-source 10.7mhz rf-source time measurement time measurement time measurement 10n ramp i2c-bus
applications 4 - 3 tua 4401k wireless components specification, 17.02.00 4401k_ spec.eps figure 4-2 application circuit
5 reference 5.1 electrical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.1 absolute maximum range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.3 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2 phase detector outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.3 bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.4 i2c bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 contents of this chapter
reference 5 - 2 tua 4401k wireless components specification, 17.02.00 5.1 electrical data 5.1.1 absolute maximum range the maximal ratings may not be exceeded under any circumstances, not even momentary and individual, as permanent damage to the ic will result. all values are referred to ground (pin), unless stated otherwise. all currents are designated according to the source and sink principle, i.e. if the device pin is to be regarded as a sink (the current flows into the stated pin to internal ground), it has a negative sign, and if it is a source (the current flows from vs across the designated pin), it has a positive sign. 5.1.2 operating range within the operational range the ic operates as described in the circuit description. the ac / dc characteristic limits are not guaranteed. table 5-1 absolute maximum range parameter symbol limit values unit min max esd-protection all bipolar pins hbm ( r=1.5k ? , c=100pf ) v esd - 1 1 kv esd-protection all cmos pins hbm ( r=1.5k ? , c=100pf ) v esd -1 1 kv total power dissipation p tot 900 mw ambient temperature t a - 40 85 c junction temperature t j 150 c storage temperature t stg - 40 125 c thermal resistance p-mqfp-44 (sys-air) t thsa 65 k/w table 5-2 operating ratings parameter symbol limit values unit test conditions litem min max supply voltage v vcc 8 9 v current consumption i vcc 111 ma ambient temperature t a - 40 85 c
reference 5 - 3 tua 4401k wireless components specification, 17.02.00 5.1.3 ac/dc characteristics ac / dc characteristics involve the spread of values guaranteed in the specified supply voltage and ambient temperature range. typical characteristics are the median of the production. table 5-3 ac/dc characteristics with t a 25 c, v vcc = 8.5 v symbol limit values unit test conditions litem min typ max power supply total current consumption i vcc 85 111 ma 1st local oscillator frequency range f 1st lo 50 250 mhz frequency range f 1st lo 50 150 mhz q factor of coil > 90 frequency range f 1st lo 160 250 mhz coil tbf; see sub06h negative input impedance z 18-19 - 1000 ? f = 100 mhz l rf mixer mixer current imix 11 14 17 ma 101 input frequency f 22-23 60 140 mhz max input rf level v 22-23 120 db v input impedance single ended r 22-23 1.8 k ? l c 22-23 2.5 pf l mixer gain a mix 12 15 18 db 259 input ip3 126 db v im = 60 db l noise figure f 6 db l reference voltage rf section v 27 4.3 4.8 5.3 v 104 prestage agc outputs agc threshold range v 22-23 48 60 72 mv see diagram sub06h 310 311 agc threshold range v 22-23 36 45 54 mv see diagram sub06h 312 313 agc threshold range v 22-23 24 30 36 mv see diagram sub06h 314 315 agc threshold range v 22-23 10 15 20 mv see diagram sub06h 316 317 agc voltage for mosfet gate 2 v 21 5.7 6.4 vv 22-23 = 0 mv 106 agc voltage for mosfet gate 2 v 21 0.1 vv 22-23 = 200 mv 300 agc current normal polarity i 24 10 13 ma v 22-23 = 0 mv 115
reference 5 - 4 tua 4401k wireless components specification, 17.02.00 table 5-3 ac/dc characteristics with t a 25 c, v vcc = 8.5 v (continued) symbol limit values unit test conditions litem min typ max agc current normal polarity i 24 0.1 ma v 22-23 = 200 mv 301 integrator current i 21 -75 -50 -25 av 22-23 = 0 mv; vm = 3v 117 integrator current i 21 25 50 75 av 22-23 = 200 mv; vm = 3v 303 if amplifier dc input voltage v 29 3.4 3.7 4.0 v 108 input resistance r 29 330 ? l output resistance r 31 330 ? l max. voltage gain a 31-29 23 26 29 db see diagram sub07h 403 min. voltage gain a 31-29 10 13 16 db see diagram sub07h 405 noise figure f 7 db r g = 330 ? if limiter amplifier / fieldstrength generator input voltage for limiter threshold v 34 25 45 v rm s f in = 10.7 mhz; v 37 - 3 db 470 am suppression a am 70 80 db m = 30 %, v 34 =100mv 469 fieldstrength voltage v 38 0.4 0.8 vv 34 = 0 mv rms 450 fieldstrength voltage v 38 1.5 1.9 2.3 vv 34 = 1 mv rms 451 fieldstrength voltage v 38 2.4 2.9 3.4 vv 34 = 10 mv rms 452 fieldstrength voltage v 38 3.6 4.2 4.8 vv 34 = 200 mv rms 471 fieldstrength dynamic range v 38dyn 90 db fieldstrength linearity v 38lin 1 db fieldstrength temperature drift v 38temp 3 db fm demodulator af output voltage v 37 500 600 720 mv rm s ? f = 75 khz; f if =10.7 mhz 455 af output voltage v 37 300 mv rm s ? f = 75 khz; f if = 21.4 mhz l total harmonic distortion thd 37 0.3 0.6 % ? f = 75 khz 456 total harmonic distortion detuned thd 37 0.8 %f in = 10.7 mhz 50 khz ; ? f = 75 khz 457
reference 5 - 5 tua 4401k wireless components specification, 17.02.00 table 5-3 ac/dc characteristics with t a 25 c, v vcc = 8.5 v (continued) symbol limit values unit test conditions litem min typ max multipath detector attack current i 40 *) 700 900 1200 av 39 = 350 mv rms ; v m = 5 v 801 recovery current i 40 *) -8 -13 -18 av 39 = 0 v rms ; v m = 3.6 v 802 start voltage v 41def 4.7 vv 39 = 0 v rms 114 detector characteristic v 41 v 41def -3.1 v v 41def -2.8 v v 41def -2.5 v vf 39 = 200 khz v 39 = 40 mv rms 800 *) detector currents are measured between the output pin (-pole) and a voltage source v m crystal oscillator operating frequency f 10-11 61.5 mhz 3rd harmonic negative input impedance z 10-11 - 250 ? f = 61.5 mhz negative input impedance z 10-11 1.4 k ? f = 20.5 mhz input impedance crystal r cr 70 ? 3rd harmonic spurious harmonics crystal a sp - 20 db f < 200 mhz bus controlled adjust range ? f adj 40 ppm see diagram sub06h bus controlled output xtal_div6 v xtal_div6 on ac 500 mv pp f = 10.25 mhz, c load = 10 pf bus controlled output xtal_div6 v xtal_div6 on dc 1.0 1.5 2.0 v dc f = 10.25 mhz, c load = 10 pf 180 bus controlled output xtal_div6 v xtal_div6 off dc 50 mv dc c load = 10 pf 197 chargepump output (loopfilter input) dc voltage v pd_0 2.3 2.5 2.7 vlocked 251 252 dc current i pd_03 3.2 45.2 ma see status, subaddress 00h, bit d1, d2 v pd_0 = 2.5v 220 to 227 dc current i pd_02 1.6 22.6 ma dc current i pd_01 0.8 11.3 ma dc current i pd_00 400 500 700 ua tristate output current i pd_0off 0.1 10 na v pd_0 = 2.5v , guaranteed by design 228 loop amplifier tuningvoltage output (loopfilter output) low output voltage v pda_l 0 400 mv i tune = 100 ua 231 high output voltage v pda_h v vcc -0.5v v cc mv i tune = -100 ua 230
reference 5 - 6 tua 4401k wireless components specification, 17.02.00 table 5-3 ac/dc characteristics with t a 25 c, v vcc = 8.5 v (continued) symbol limit values unit test conditions litem min typ max high output current source i pda_h -1.9 -2.4 -2.9 ma v tune = 4v, v pd_0 = 0v (see status, subaddress 00h, bit d11) 232 233 low output current source i pda_l -0.9 -1.2 -1.5 ma pll for synthesizer (see pll synthesizer on page 3-16) pll / vco step size (programmable via r- counter) f ref 6.25 100 khz f crystal = 61.5 mhz n-counter divide ratio n2 65535 16-bit 200 to 207 r-counter divide ratio r2 65535 16-bit 210 to 216 port outputs, port_1, port_2, if_cent, if_window (see output ports on page 3-15) low output voltage v p 0 100 400 mv i p = 1 ma *1) high leakage current i p_leack 0 100 na v p = 5 v *2) *1) 830, 840, 831, 834 *2) 118, 119, 124, 125 i 2 c bus (scl, sda) (see i2c bus timing on page 5-12 and bus data format on page 3-15) h-input voltage v ih 2.10 5.50 v 150 l-input voltage v il -0.5 0.90 v 150 hysteresis of schmitt trigger inputs (scl, sda) v hys 0.30 v input capacity c i 5 pf i 2 c bus leakage current i _leack 0 1 a values only valid for applied v cc l ref voltages ref voltage v 6 4.5 5.0 5.5 v 102 ref voltage v 7 2.7 3.0 3.3 v 103
reference 5 - 7 tua 4401k wireless components specification, 17.02.00 5.2 phase detector outputs pd_o f r f n p-channel tri-state. polarity pos. frequency f n > f r or f v leading frequency f n = f r frequency f n < f r or f v lagging n-channel
reference 5 - 8 tua 4401k wireless components specification, 17.02.00 5.3 bus interface 1. bus interface i 2 c bus 2. bus data format i 2 c bus write mode i 2 c bus read mode 1): mandatory low send by up, 2): mandatory high send by up chipaddress organisation subaddress organisation msb chip address (write) lsb msb sub address (write) 00h...07h, 0bh lsb msb data in x...0 (x=7 or 15) lsb sta 11001100 ack s7 s6 s5 s4 s3 s2 s1 s0 ack dx ... d5 d4 d3 d2 d1 d0 ack sto msb chip address (write) lsb msb sub address (read) 82h/83h lsb msb chip address (read) lsb sta 11001100 ack 10000010 ack sta 11001101 ack msb data out from sub add 82h lsb msb data out from sub add 82h/83h lsb r15 r14 r13 r12 r11 r10 r9 r8 ack 1) r7 r6 r5 r4 r3 r2 r1 r0 ack 2) sto chip address msb lsb function 11001100chip address write 11001101chip address read sub addresses of data registers write msb bin lsb hex function 0000000000hstatus 00000001 01h r_counter 00000010 02h n_counter 00000011 03h mute_dac7 00000100 04h if_count_p1 00000101 05h if_count_p2 00000110 06h specials 00000111 07h gain_dac4 00001011 0bh comp-preset sub address of data register read msb bin lsb hex function 1000001082h result multipath, fieldstrength, if_window and if_center 1000001183hresult-misc
reference 5 - 9 tua 4401k wireless components specification, 17.02.00 data byte specification status subaddress 00h r_counter subaddress 01h n_counter subaddress 02h results fieldstrength, multipath and if counter subaddress 82h (read address) bit function bit function bit function bit function msb d15 not used (must be=0) msb d15 2 15 msb d15 2 15 msb d15 if_window d14 port_2 (0=low, 1=high) d14 2 14 d14 2 14 d14 multipath_2 6 d13 port_1 (0=low, 1=high) d13 2 13 d13 2 13 d13 multipath_2 5 d12 not used (must be=0) d12 2 12 d12 2 12 d12 multipath_2 4 d11 loopamp current d11 2 11 d11 2 11 d11 multipath_2 3 d10 not used (must be=0) d10 2 10 d10 2 10 d10 multipath_2 2 d9 not used (must be=0) d9 2 9 d9 2 9 d9 multipath_2 1 d8 not used (must be=0) d8 2 8 d8 2 8 d8 multipath_2 0 d7 adc_single d7 2 7 d7 2 7 d7 if_center d6 adc_mode d6 2 6 d6 2 6 d6 fieldstrength_2 6 d5 adc_on d5 2 5 d5 2 5 d5 fieldstrength_2 5 d4 if_dac4 d4 2 4 d4 2 4 d4 fieldstrength_2 4 d3 not used (must be=0) d3 2 3 d3 2 3 d3 fieldstrength_2 3 d2 cp_current 2 d2 2 2 d2 2 2 d2 fieldstrength_2 2 d1 cp_current 1 d1 2 1 d1 2 1 d1 fieldstrength_2 1 d0 lsb cp_mode d0 lsb 2 0 d0 lsb 2 0 d0 lsb fieldstrength_2 0 mute_dac7 subaddress 03h if_count_p1 subaddress 04h if_count_p2 subaddress 05h specials subaddress 06h if_dac4 subaddress 07h comp_preset subaddress 0bh bit function bit function bit function bit function bit function bit function msb d7 enable msb d7 enable msb d7 cf_mod e msb d7 xtal_div6 msb d7 not used msb d15 not used d6 mdac_6 d6 not used d6 cf_6 d6 vco_2 d6 not used d14 fieldstrength_2 6 d5 mdac_5 d5win_2 d5cf_5 d5agc_1 d5 not used d13 fieldstrength_2 5 d4 mdac_4 d4win_1 d4cf_4 d4agc_0 d4 not used d12 fieldstrength_2 4 d3 mdac_3 d3 win_0 d3 cf_3 d3 xtal_3 d3 gdac_3 d11 fieldstrength_2 3 d2 mdac_2 d2 gate_2 d2 cf_2 d2 xtal_2 d2 gdac_2 d10 fieldstrength_2 2 d1 mdac_1 d1 gate_1 d1 cf_1 d1 xtal_1 d1 gdac_1 d9 fieldstrength_2 1 d0 lsb mdac_0 d0 lsb gate_0 d0 lsb cf_0 d0 lsb xtal_0 d0 lsb gdac_0 d8 fieldstrength_2 0 d7 not used result misc subaddress 83h d6 multipath_2 6 bit function d5 multipath_2 5 msb d7 if_window d4 multipath_2 4 d6 if_center d3 multipath_2 3 d5 fieldstrength_comp d2 multipath_2 2 d4 multipath_comp d1 multipath_2 1 d3 res d0 lsb multipath_2 0 d2 res
reference 5 - 10 tua 4401k wireless components specification, 17.02.00 d1 res d0 lsb res status, subaddress 00h msb lsb msb lsb function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 these bits must be = 0 01 opendrain port_2 output = high level 00 opendrain port_2 output = low level 01 opendrain port_1 output = high level 00 opendrain port_1 output = low level 01 loopamp currentsource high (i loopamp =2.4ma) for high speed tuning 0 0 loopamp currentsource low (i loopamp =1.2ma) 0 0 0 1 7 bit ad converter enabled for single mode, stop 0101 7 bit ad converter enabled for single mode start. to restart single mode write the same bits once more. 0 0 1 1 7 bit ad converter enabled for continuous mode run. 0xx1 7 bit ad converter enabled for single or continuous mode 0xx0 7 bit ad converter disabled for single and continuous mode 0 1 if_dac4 enabled (see subaddress 07h) 0 0 if_dac4 disabled (see subaddress 07h) 0 1 1 chargepump current i cp3 = 4ma 0 1 0 chargepump current i cp2 = 2ma 0 0 1 chargepump current i cp1 = 1ma 0 0 0 chargepump current i cp0 = 500ua 0 1 chargepump enabled 0 0 chargepump disabled subaddress 01h, r_counter and subaddress 02h, n_counter msb lsb msb lsb function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 1 11 1 1111111 divider by 65535 0 0 0 0 0 1 11 1 1010000 divider by 2000 0 0 0 0 0 1 00 1 1001110 divider by 1230 0 0 0 0 0 0 11 1 1101000 divider by 1000 0 0 0 0 0 0 10 0 1100111 divider by 615 0 0 0 0 0 0 00 0 1100100 divider by 100 0 0 0 0 0 0 00 0 0001010 divider by 10 0 0 0 0 0 0 00 0 0000010 divider by 2
reference 5 - 11 tua 4401k wireless components specification, 17.02.00 subaddress 03h, mute_dac7 subaddress 05h, if_count_p2, centerfrequency = cf, cf step = 6.25khz) / 12.5 khz msb lsb function msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 centerfrequency cf1 0 centerfrequency cf0 1 1111111 not used (must be 1) 1 1111111 cf1= 22.3875 mhz 0 1111111 cf0= 11.1937 mhz subaddress 04h, if_count_p1 msb lsb function 1 1000000 cf1= 22.600 mhz d7d6d5d4d3d2d1d0 0 1000000 cf0= 10.800 mhz 1 if_count enabled 0 if_count disabled 1 0110001 cf1= 21.4125 mhz 0 not used (must be=0) 0 0110001 cf0= 10.70625 mhz 100 window=+/-100khz* 1 0110000 cf1= 21.400 mhz 011 window=+/-50khz* 0 0110000 cf0= 10.700 mhz 010 window=+/-25khz* 1 0101111 cf1= 21.3875 mhz 001 window=+/-12.5khz* 0 0101111 cf0= 10.69375 mhz 0 0 0 window=+/-6.25khz* 111 gatetime= 40.96ms 1 0100000 cf1= 21.200 mhz 110 gatetime= 20.48ms 0 0100000 cf0= 10.600 mhz 1 0 1 gatetime= 10.24ms 100 gatetime= 5.12ms 1 0010000 cf1= 21.000 mhz 011 gatetime= 2.56ms 0 0010000 cf0= 10.500 mhz 0 1 0 gatetime= 1.28ms 001 gatetime= 640us 1 0000000 cf1= 20.800 mhz 000 gatetime= 320us 0 0000000 cf0= 10.400 mhz * valid for d7= 0 in subaddress 05h centerfrequencies for multiply window value with 2 for d7= 1 in subaddress 05h d7=1 cf1= 20.800 mhz +n*12.5 khz, cf step =12.5 khz (e. g. d7= 0 window =+/- 6.25 khz d7=0 cf0= 10.400 mhz +n*6.25 khz, cf step =6.25 khz d7= 1 window =+/- 12.5 khz) n=0...127
reference 5 - 12 tua 4401k wireless components specification, 17.02.00 *) for continuous tuning characteristic it is recommended to skip steps 8 and 9 subaddress 06h, specials subaddress 07h, if_dac4 msb lsb function msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 xtal_div6 enabled x x x x not used 0 xtal_div6 disabled 1111 if_dac gain adj. typ. 16 db 1 1st lo divided by 1 1110 if_dac gain adj. 0 1st lo divided by 2 1101 if_dac gain adj. 00 prest. agc threshold typ. 15 mv 1100 if_dac gain adj. 01 prest. agc threshold typ. 30 mv 1011 if_dac gain adj. typ. 21 db 10 prest. agc threshold typ. 45 mv 1010 if_dac gain adj. 11 prest. agc threshold typ. 60 mv 1001 if_dac gain adj. 1111 xtal_adjust c l = 15 pf 1000 if_dac gain adj. 1110 xtal_adjust c l = 14pf 0111 if_dac gain adj. 1101 xtal_adjust c l = 13 pf 0110 if_dac gain adj. 1100 xtal_adjust c l = 12 pf 0101 if_dac gain adj. 1011 xtal_adjust c l = 11 pf 0100 if_dac gain adj. typ. 24 db 1010 xtal_adjust c l = 10 pf 0011 if_dac gain adj. 1001 xtal_adjust c l = 9 pf *) 0010 if_dac gain adj. 1000 xtal_adjust c l = 8 pf *) 0001 if_dac gain adj. 0111 xtal_adjust c l = 7 pf 0000 if_dac gain adj. typ. 26 db 0110 xtal_adjust c l = 6 pf 0101 xtal_adjust c l = 5 pf 0100 xtal_adjust c l = 4 pf 0011 xtal_adjust c l = 3 pf 0010 xtal_adjust c l = 2 pf 0001 xtal_adjust c l = 1pf 0000 xtal_adjust c l = 0pf subaddress 0bh, comp preset msblsbmsblsb function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x not used fp2 6 fp2 5 fp2 4 fp2 3 fp2 2 fp2 1 fp2 0 preset value fieldstrength mp2 6 mp2 5 mp2 4 mp2 3 mp2 2 mp2 1 mp2 0 preset value multipath
reference 5 - 13 tua 4401k wireless components specification, 17.02.00 5.4 i 2 c bus timing subaddress 82h, read results from fieldstrength, multipath and if counter msb lsb msb lsb function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 11 if_counter result: if frequency is outside the desired window. if frequency is lower as the desired if frequency. 01 if_counter result: if frequency is outside the desired window.if frequency is higher as the desired if frequency. x0 if_counter result: if frequency is inside the desired window m2 6 m2 5 m2 4 m2 3 m2 2 m2 1 m2 0 result multipath byte m6...m0 f2 6 f2 5 f2 4 f2 3 f2 2 f2 1 f2 0 result fieldstrength byte f6...f0 subaddress 83h, read results misc msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 1 1 res res res res if_counter result: if frequency is outside the desired window. if frequency is lower as the desired if frequency. 0 1 res res res res if_counter result: if frequency is outside the desired window.if frequency is higher as the desired if frequency. x 0 res res res res if_counter result: if frequency is inside the desired window 1 fieldstrength is higher as the preseted value in subaddress 0bh (d8...d14) 0 fieldstrength is lower as the preseted value in subaddress 0bh (d8...d14) 1 multipathsignal is higher as the preseted value in subaddress 0bh (d0...d6) 0 multipathsignal signal is lower as the preseted value in subaddress 0bh (d0...d6) scl sda t buf s p t hd.dat t hd.sta t high t f t low t r t su.dat t hd.sta t sp p t su.sto s t su.sta bus_mode = low
reference 5 - 14 tua 4401k wireless components specification, 17.02.00 2) c b = capacitance of one bus line in pf. note that the maximum t f for the sda and scl bus lines quoted at 300ns is longer than the specified maximum t of for the output stages (250ns).this allows series protection resistors to be connected between the sda / scl pins and the sda /scl bus lines without exceeding the maximum specified t f . table 5-4 parameter symbol min max unit low level input voltage (sda, scl) v il -0.5 0.90 v high level input voltage (sda, scl) v ih 2.10 5.50 v pulse width of spikes which must be suppressed by the input fil- ter t sp 0 50 ns low level output voltage 3ma sink current (sda) v ol 0 0.40 v output fall time from v ihmin to v ilmax with a bus capacitance from 10pf to 400pfwith up to 3ma t of 20+0.1c b 2) 250 ns scl clock frequency f scl 0 400 khz bus free time between a stop and start condition t buf 1.3 s hold time (repeated) start condition. after this period, the first clock pulse is generated. t ho.sta 0.6 s low period of the scl clock t low 1.3 s high period of the scl clock t high 0.6 s set-up time for a repeated start condition t su.sta 0.6 s data hold time t hd.dat 0 ns data set -up time t su.dat 100 ns rise, fall time of both sda and scl signals t r , t f 20+0.1c b 2) 300 ns set-up time for stop condition t su.sto 0.6 s capacitive load for each bus line c b 400 pf

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